The present invention relates to multi-processor data communications systems and more particularly to a structure for the data bus of such a system.
The invention is particularly applicable to microprocessor based controllers for the automatic control of processes where a relatively large number of control loops are involved and it is desired to have a distributed control system.
In a system environment which involves a multiprocessor shared resource configuration, the resource, such as a read only memory (RAM) or a programmed random access memory (PROM), must be put in communication with a selected one of the processors by way of a data bus in the priority ranking of the requesting units. The classical means for accomplishing the transfer of data between the processors and the resource or between the processors themselves involves the granting of access to the data bus to one of the processors with that processor retaining control for its complete data transfer. Thus, if a complete data transfer involved the transfer of three words, that is, three bytes of contiguous information, for example, and the transfer involves one word at a time, the time necessary to accomplish the transfer would include not only the time necessary to transfer sequentially the three bytes but also the time necessary to calculate the address of the second and third bytes. With such an arrangement a processor requesting access would have to wait not only during the sequential period in which the three bytes are transferred but also during the calculation phase. This, of course, slows down the data transfer and ties up the system resources.
The present invention provides a bus structure which avoids the disadvantages of the classical means for transfering multiple data words in multi-processor shared resource environments so that there will be an increased bus utilization and a decrease in the bus wait time.